The present invention relates to the field of programmable logic devices, and more particularly, to interconnection resources for programmable logic devices.
Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user. Altera's FLEX.RTM. line of programmable logic are among the most advanced and successful programmable logic devices. The FLEX architecture provides a large matrix of small logic elements (also known as macrocells) that can be programmably configured and interconnected to provide desired logic functions.
In many programmable logic devices, for example, a number of logic elements are arranged in groups to form larger entities referred to as logic array blocks ("LABs"). The various LABs are arranged in a two-dimensional array and are connectable to each other and to I/O pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as horizontal interconnect and vertical interconnect or collectively as "global" interconnect lines. In Altera's line of production these may include what are referred to as "Horizontal FastTracks.TM." and "Vertical FastTracks.TM.."
Each logic element can perform various combinational and registered logical operations. A local interconnect resource is also provided to allow the logic elements in a LAB to share signals without using the global interconnection resources. Additional detail regarding the FLEX devices may be found, for example, in Altera's Data Book, January 1998, along with U.S. Pat. Nos. 5,260,610 and 5,260,611, all of which are incorporated herein by reference for all purposes.
These logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, a large portion of the delay in the critical path is due to delay in the interconnect resources. A certain amount of delay exists in the connection between the global interconnect structure and the LABs. Thus a faster global interconnect can increase the overall system performance significantly.
Another aspect of programmable logic integrated circuits that may be improved is the programming flexibility of the interconnect resources in the logic device. In currently available devices, a signal may be routed from a vertical conductor to a horizontal conductor without passing through a logic element, but for a signal to be routed from a horizontal conductor to a vertical conductor, it must pass through a logic element. Also, currently available devices do not provide complete flexibility in routing between horizontal and vertical lines. For example, at a particular junction, a vertical conductor may only be connected to a single horizontal conductor. It is desirable to be able to select from among a plurality of vertical conductors as the destination, thereby increasing the routing flexibility of the logic device.
For at least the above reasons, a PLD which provides faster and more flexible interconnect resources is needed.